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S29WS128J/064J
128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.11 m process technology Simultaneous Read/Write operation -- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations -- Four bank architecture: WS128J: 16Mb/48Mb/48Mb/ 16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb Programable Burst Interface -- 2 Modes of Burst Read Operation -- Linear Burst: 8, 16, and 32 words with wrap-around -- Continuous Sequential Burst Secured Silicon Sector region -- 128 words accessible through a command sequence, 64words for the Factory Secured Silicon Sector and 64words for the Customer Secured Silicon Sector. Sector Architecture 4 Kword x 16 boot sectors, eight at the top of the address range, and eight at the bottom of the address range -- WS128J: 4 Kword X 16, 32 Kword x 254 sectors Bank A : 4 Kword x 8, 32 Kword x 31 sectors Bank B : 32 Kword x 96 sectors Bank C : 32 Kword x 96 sectors Bank D : 4 Kword x 8, 32 Kword x 31 sectors -- WS064J: 4 Kword x 16, 32 Kword x 126 sectors. Bank A : 4 Kword x 8, 32 Kword x 15 sectors Bank B : 32 Kword x 48 sectors Bank C : 32 Kword x 48 sectors Bank D : 4 Kword x 8, 32 Kword x 15 sectors WS128J : 84-ball (8 mm x 11.6 mm) FBGA package, WS064J : 80-ball (7 mm x 9 mm) FBGA package Cyclling Endurance : 1,000,000 cycles per sector typical Data retention : 20-years typical
Hardware Features
Handshaking feature available -- Provides host system with minimum possible latency by monitoring RDY Hardware reset input (RESET#) -- Hardware method to reset the device for reading array data WP# input -- Write protect (WP#) function allows protection of four outermost boot sectors, regardless of sector protect status Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL CMOS compatible inputs, CMOS compatible outputs Low VCC write inhibit
Software Features
Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards -- Backwards compatible with Am29BDS, Am29BDD, Am29BL, and MBM29BS families Data# Polling and toggle bits -- Provides a software method of detecting program and erase operation completion Erase Suspend/Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences
Performance Characteristics
Read access times at 80/66 MHz -- Synchronous latency of 71/56 ns (at 30 pF) -- Asynchronous random access times of 55/55 ns (at 30 pF) Power dissipation (typical values, CL = 30 pF) -- Burst Mode Read: 18 mA @ 80Mhz -- Simultaneous Operation: 60 mA @ 80Mhz -- Program/Erase: 15 mA -- Standby mode: 0.2 A
Publication Number S29WS-J_00
Revision A
Amendment 6
Issue Date May 11, 2006
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
Data
Sheet
General Description
The S29WS128J/064J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0volt VHH on ACC may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers. At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency of 56 ns at 30 pF. The device operates within the wireless temperature range of -25C to +85C, and is offered in Various FBGA packages. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Quantity Bank A B C D 128Mb 8 31 96 96 31 8 64 Mb 8 15 48 48 15 8 Size 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase or program on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. Program suspend is also offered.
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The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the four outermost boot sectors. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. SpansionTM Flash memory products combine years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
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Data
Sheet
Table of Contents
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii Preliminary ..........................................................................................................ii Combination .......................................................................................................ii Full Production (No Designation on Document) ...................................ii
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 46
Reading Array Data ...........................................................................................46 Set Configuration Register Command Sequence ..................................... 47
Figure 4. Synchronous/Asynchronous State Diagram .............. 48
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram of Simultaneous Operation Circuit 7 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Special Handling Instructions for FBGA Package ........................................8
Read Mode Setting .........................................................................................48 Programmable Wait State Configuration ...............................................48
Table 14. Programmable Wait State Settings .........................49
Standard wait-state Handshaking Option ...............................................49
Table 15. Wait States for Standard wait-state Handshaking ....49
Read Mode Configuration ...........................................................................50
Table 16. Read Mode Settings ..............................................50
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12
128 Mb Products based on 110 nm Floating Gate Technology ................13 64 Mb Products based on 110 nm Floating Gate Technology .................13
Burst Active Clock Edge Configuration ..................................................50 RDY Configuration ........................................................................................ 50 Configuration Register ......................................................................................50
Table 17. Configuration Register ..........................................51
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 14
Table 1. Device Bus Operations .......................................... 14
Requirements for Asynchronous ReadOperation (Non-Burst) ........... 14 Requirements for Synchronous (Burst) Read Operation ....................... 14 8-, 16-, and 32-Word Linear Burst with Wrap Around .......................15
Table 2. Burst Address Groups ............................................ 15
Reset Command .................................................................................................. 51 Autoselect Command Sequence .................................................................... 51 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence .................................................................................................................... 52 Program Command Sequence .........................................................................53 Unlock Bypass Command Sequence .........................................................53
Figure 5. Program Operation ............................................... 54
Configuration Register ...................................................................................... 16 Handshaking .......................................................................................................... 16 Simultaneous Read/Write Operations with Zero Latency .................... 16 Writing Commands/Command Sequences ................................................. 16 Accelerated Program Operation ....................................................................17 Autoselect Mode ..................................................................................................17
Table 3. Autoselect Codes (High Voltage Method) ................. 18
Chip Erase Command Sequence ................................................................... 54 Sector Erase Command Sequence ................................................................ 55 Erase Suspend/Erase Resume Commands .................................................. 55
Figure 6. Erase Operation ................................................... 56
Sector/Sector Block Protection and Unprotection .................................. 18
Table 4. S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection ..................................................... 18 Table 5. S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection ..................................................... 21
Advanced Sector Protection/Unprotection . . . . 23
Figure 1. Advanced Sector Protection/Unprotection................. 23
Lock Register ....................................................................................................... 24
Table 6. Lock Register ........................................................ 24
Persistent Protection Bits ................................................................................ 24
Figure 2. PPB Program/Erase Algorithm................................. 26
Password Program Command ....................................................................... 57 Password Verify Command ............................................................................. 57 Password Protection Mode Locking Bit Program Command .............. 57 Persistent Sector Protection Mode Locking Bit Program Command 57 Secured Silicon Sector Protection Bit Program Command .................. 58 PPB Lock Bit Set Command ............................................................................ 58 DPB Write/Erase/Status Command ............................................................. 58 Password Unlock Command .......................................................................... 58 PPB Program Command .................................................................................. 59 All PPB Erase Command .................................................................................. 59 PPB Status Command ....................................................................................... 59 PPB Lock Bit Status Command ...................................................................... 59 Command Definitions .......................................................................................60
Table 18. Command Definitions ..........................................60
Dynamic Protection Bits .................................................................................. 26 Persistent Protection Bit Lock Bit .................................................................27 Password Protection Method .........................................................................27
Figure 3. Lock Register Program Algorithm ............................ 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 62
DQ7: Data# Polling ........................................................................................... 62
Figure 7. Data# Polling Algorithm ........................................ 63
Advanced Sector Protection Software Examples .................................... 29
Table 7. Sector Protection Schemes ..................................... 29
RDY: Ready .......................................................................................................... 63 DQ6: Toggle Bit I ...............................................................................................64
Figure 8. Toggle Bit Algorithm ............................................. 65
Hardware Data Protection Methods ........................................................... 29 WP# Method .................................................................................................. 29 ACC Method ................................................................................................... 29 Low VCC Write Inhibit ................................................................................. 29 Write Pulse "Glitch Protection" ............................................................... 30 Power-Up Write Inhibit ............................................................................... 30
DQ2: Toggle Bit II .............................................................................................. 65
Table 19. DQ6 and DQ2 Indications ......................................66
Reading Toggle Bits DQ6/DQ2 .....................................................................66 DQ5: Exceeded Timing Limits ........................................................................66 DQ3: Sector Erase Timer ................................................................................ 67
Table 20. Write Operation Status .........................................67
Common Flash Memory Interface (CFI) . . . . . . 30
Table 8. CFI Query Identification String ................................ 30 Table 9. System Interface String ......................................... 31 Table 10. Device Geometry Definition .................................. 31 Table 11. Primary Vendor-Specific Extended Query ................ 32 Table 12. WS128J Sector Address Table ............................... 33 Table 13. WS064J Sector Address Table ............................... 41
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 68
Figure 9. Maximum Negative Overshoot Waveform................. 68 Figure 10. Maximum Positive Overshoot Waveform ................ 68
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 69
Commercial (C) Devices ............................................................................. 69 Wireless (W) Devices ..................................................................................69 Supply Voltages ...............................................................................................69
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DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 70 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 11. Test Setup ......................................................... 71 Table 21. Test Specifications ............................................... 71
Key to Switching Waveforms . . . . . . . . . . . . . . . 71 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 71
Figure 12. Input Waveforms and Measurement Levels............. 71
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 72
VCC Power-up ......................................................................................................72 CLK Characterization ........................................................................................72
Figure 13. VCC Power-up Diagram ........................................ 72 Figure 14. CLK Characterization ........................................... 72
Figure 26. Synchronous Program Operation Timings: CLK Latched Addresses ......................................................................... 84 Figure 27. Chip/Sector Erase Command Sequence ................. 85 Figure 28. Accelerated Unlock Bypass Programming Timing..... 86 Figure 29. Data# Polling Timings (During Embedded Algorithm) 86 Figure 30. Toggle Bit Timings (During Embedded Algorithm) ... 87 Figure 31. Synchronous Data Polling Timings/Toggle Bit Timings 87 Figure 32. DQ2 vs. DQ6...................................................... 88
Temporary Sector Unprotect ........................................................................88
Figure 33. Temporary Sector Unprotect Timing Diagram ......... 88 Figure 34. Sector/Sector Block Protect and Unprotect Timing Diagram ........................................................................... 89 Figure 35. Latency with Boundary Crossing ........................... 89 Figure 36. Latency with Boundary Crossing into Program/Erase Bank ........................................................................................90 Figure 37. Example of Wait States Insertion .......................... 91 Figure 38. Back-to-Back Read/Write Cycle Timings................. 92
Synchronous/Burst Read ...................................................................................73
Figure 15. CLK Synchronous Burst Mode Read (rising active CLK). ....................................................................................... 74 Figure 16. CLK Synchronous Burst Mode Read (Falling Active Clock) ....................................................................................... 75 Figure 17. Synchronous Burst Mode Read.............................. 75 Figure 18. 8-word Linear Burst with Wrap Around................... 76 Figure 19. Linear Burst with RDY Set One Cycle Before Data.... 76
Erase and Programming Performance . . . . . . . . 93 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 94
VBH084 - 84-ball Fine-Pitch Ball Grid Array (FBGA) 8x11.6 mm MCP Compatible Package (128Mb) .......................................................................... 94 VBR080 - 80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm (64Mb) ................................................................................................................................... 95
Asynchronous Mode Read ...............................................................................77
Figure 20. Asynchronous Mode Read with Latched Addresses... 77 Figure 21. Asynchronous Mode Read..................................... 78
Hardware Reset (RESET#) .............................................................................. 78
Figure 22. Reset Timings..................................................... 79
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 96
Revision A0 (July 22, 2004) ............................................................................. 96 Revision A1 (October 6, 2004) .......................................................................96 Revision A2 (December 10, 2004) .................................................................96 Revision A3 (February 19, 2005) ....................................................................96 Revision A4 (June 24, 2005) ............................................................................96 Revision A5 (March 31, 2006) ......................................................................... 96 Revision A6 (April 28, 2006) .......................................................................... 97
Erase/Program Operations .............................................................................80
Figure 23. Asynchronous Program Operation Timings: AVD# Latched Addresses ............................................................. 81 Figure 24. Asynchronous Program Operation Timings: WE# Latched Addresses ......................................................................... 82 Figure 25. Synchronous Program Operation Timings: WE# Latched Addresses ......................................................................... 83
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Product Selector Guide
Synchronous/Burst Speed Option Max Latency, ns (tIACC) Max Burst Access Time, ns (tBACC) Max OE# Access, ns (tOE) 66 MHz 56 11.2 11.2 80 MHz (Note) 71 9.1 9.1
Asynchronous Speed Option Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) 66 MHz 55 55 11.2 80 MHz (Note) 55 55 9.1
Note: 80 MHz option is available for S29WS064J only.
Block Diagram
VCC VSS VSSIO RDY Buffer RDY Erase Voltage Generator Input/Output Buffers DQ15-DQ0
WE# RESET# WP# ACC
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic Data Latch
CE# OE#
Y-Decoder VCC Detector
Y-Gating
Address Latch
Timer
X-Decoder
Cell Matrix
AVD# CLK
Burst State Control
Burst Address Counter
Amax-A0 Amax: WS064J (A21), WS128J (A22)
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Block Diagram of Simultaneous Operation Circuit
VCC VSS VSSIO
Y-Decoder
Bank A Address
Latches and Control Logic
DQ15-DQ0
Bank A
Amax-A0 X-Decoder OE#
Bank B Address
Latches and Control Logic
Y-Decoder
DQ15-DQ0
Bank B
WP# ACC RESET# WE# CE# AVD# RDY DQ15-DQ0
Amax-A0
X-Decoder DQ15-DQ0 Status
STATE CONTROL & COMMAND REGISTER
Amax-A0
Control
X-Decoder
Latches and Control Logic
Y-Decoder
Bank C Address
Bank C
DQ15-DQ0
Amax-A0
Amax-A0 X-Decoder
Bank D Address
Latches and Control Logic
Y-Decoder
Bank D
DQ15-DQ0
Note: Amax: WS064J (A21), WS128J (A22)
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Connection Diagram
S29WS064J 80-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 AVD# B1 WP# C1 A3 D1 A2 E1 A1 F1 A0 G1 CE#f1 H1 RFU J1 RFU K1 RFU
A2 RFU B2 A7 C2 A6 D2 A5 E2 A4 F2 VSS G2 OE# H2 DQ0 J2 DQ8 K2 RFU
A3 CLK B3 RFU C3 RFU D3 A18 E3 A17 F3 DQ1 G3 DQ9 H3 DQ10 J3 DQ2 K3 RFU
A4 RFU B4 ACC C4 RESET# D4 RDY E4 RFU F4 RFU G4 DQ3 H4 VCC J4 DQ11 K4 VCC
A5 RFU B5 WE# C5 RFU D5 A20 E5 RFU F5 RFU G5 DQ4 H5 RFU J5 RFU K5 RFU
A6 RFU B6 A8 C6 A19 D6 A9 E6 A10 F6 DQ6 G6 DQ13 H6 DQ12 J6 DQ5 K6 RFU
A7 RFU B7 A11 C7 A12 D7 A13 E7 A14 F7 RFU G7 DQ15 H7 DQ7 J7 DQ14 K7 RFU
A8 RFU B8 RFU C8 A15 D8 A21 E8 RFU F8 A16 G8 RFU H8 VSS J8 RFU K8 RFU
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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Connection Diagram
S29WS128J-MCP Compatible 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 NC B2 AVD# C2 WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f1 J2 RFU K2 RFU L2 RFU M1 NC B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 RFU D4 RFU E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU B5 RFU C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCC K5 DQ11 L5 VCC B6 RFU C6 WE# D6 RFU E6 A20 F6 RFU G6 RFU H6 DQ4 J6 RFU K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU
A10 NC
M10 NC
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Input/Output Descriptions
Amax-A0 DQ15-DQ0 CE# OE# WE# VCC VSS NC RDY = = = = = = = = = Address inputs Data input/output Chip Enable input. Asynchronous relative to CLK for the Burst mode. Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Device Power Supply (1.65 - 1.95 V). Ground No Connect; not connected internally Ready output; In Synchronous Mode, indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. In Asynchronous Mode, indicates the status of the internal program and erase function. Low = program/erase in progress. High Impedance = program/erase completed. CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Address Valid input. Indicates to device that the valid address is present on the address inputs (Amax-A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions.
CLK
=
AVD#
=
RESET# WP#
= =
ACC
=
Note:
1. Amax = A22 (WS128J), A21 (WS064J).
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Logic Symbol
max*+1 Amax-A0 CLK WP# ACC CE# OE# WE# RESET# AVD# RDY DQ15-DQ0 16
*Max = 22 for the WS128J and 21 for the WS064J.
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Ordering Information
The order number (Valid Combination) is formed by the following: S 29 W S ### J ## X X X ## #
Packing Type
0 2 3 = Tray = 7" Tape & Reel = 13" Tape & Ree
Additional Ordering Options
00 01 10 11 : : : : Die Die Die Die Revision Revision Revision Revision 0, 0, 1, 1, Dual Boot Protection None Boot Protection Dual Boot Protection None Boot Protection
Temperature Grade
W I = Wireless (-25 to + 85 C) = Industrial (-40 to + 85 C)
Package Material Set (BGA Package Type)
A F = Lead (Pb)-Free Compliant Package = Standard Lead (Pb)-Free Package
Package Type
B 0S 0P = BGA Package
Speed Option
= 80 MHz (WS064J only) = 66 MHz
Process Technology
J = 110 nm Floating Gate Technology
Density
Flash density 128 = 128 Mb 064 = 64 Mb
Core Voltage
S W 29 = 1.8-volt VCC = Burst, Simultaneous Read/Write
Flash Interface and Simultaneous Read/Write Product Series
= Sector Erase NOR Flash memory
Prefix
S = SpansionTM
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128 Mb Products based on 110 nm Floating Gate Technology
Valid Combinations for FBGA Packages S29WS128J0PBAW00 S29WS128J0PBAW01 S29WS128J0PBAW10 S29WS128J0PBAW11 S29WS128J0PBAI10 S29WS128J0PBAI11 S29WS128J0PBFW00 S29WS128J0PBFW01 S29WS128J0PBFW10 S29WS128J0PBFW11 S29WS128J0PBFI10 S29WS128J0PBFI11 Package Marking WS128J0PBAW00 WS128J0PBAW01 WS128J0PBAW10 WS128J0PBAW11 WS128J0PBAI10 WS128J0PBAI11 WS128J0PBFW00 WS128J0PBFW01 WS128J0PBFW10 WS128J0PBFW11 WS128J0PBFI10 WS128J0PBFI11 (-40 - +85 C) (-25 - +85 C) (-40 - +85 C) 66 MHz (-25 - +85 C) Temperature Burst Speed Boot Protect Dual None Dual None Dual None Dual None Dual None Dual None
Standard Lead (Pb)Free Package Lead (Pb)Free Compliant Package
Package Material Set
Package Type
84 - ball 8mm x 11.6mm MCP Compatible
64 Mb Products based on 110 nm Floating Gate Technology
Valid Combinations for FBGA Packages S29WS064J0PBAW00 S29WS064J0SBAW00 S29WS064J0PBAW01 S29WS064J0SBAW01 S29WS064J0PBFW00 S29WS064J0SBFW00 S29WS064J0PBFW01 S29WS064J0SBFW01 Package Marking WS064J0PBAW00 WS064J0SBAW00 WS064J0PBAW01 WS064J0SBAW01 WS064J0PBFW00 WS064J0SBFW00 WS064J0PBFW01 WS064J0SBFW01 Temperature (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) (-25 - +85 C) Burst Speed 66 MHz 80 MHz 66 MHz 80 MHz 66 MHz 80 MHz 66 MHz 80 MHz Boot Protect Dual None Dual None
Package Material Set
Lead (Pb)Free Compliant Package Standard Lead (Pb)Free Package
Package Type
80 - ball 7mm x 9mm MCP Compatible
Valid Combinations Valid Combination configuration planned to be supported for this device.
Notes: 1.80 MHz operation has a different Vcc(+1.70V to 1.95V).
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Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset CE# L L L L H X
Device Bus Operations
OE# L L H H X X WE# H H L L X X A22-0 Addr In Addr In Addr In Addr In HIGH Z HIGH Z DQ15-0 I/O I/O I/O I/O HIGH Z HIGH Z RESET# H H H H H L X X X X CLK (See Note) X X X L L AVD#
Burst Read Operations
Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L X L X X X H H H H H Addr In HIGH Z HIGH Z HIGH Z HIGH Z X Burst Data Out HIGH Z HIGH Z I/O H H H L H X H X X
Legend: L = Logic 0, H = Logic 1, X = Don't Care Note: Default active edge of CLK is the rising edge.
Requirements for Asynchronous ReadOperation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax- A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15-DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation.
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Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See "Set Configuration Register Command Sequence" section on page 47 and "Command Definitions" section on page 46 for further details. Once the system has written the "Set Configuration Register" command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency (WS128J/064J model numbers 00 and 01) or a three cycle latency (WS128J model numbers 10 and 11) occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). Additionally, when the device is read from an odd address, one wait state is inserted when the address pointer crosses the first boundary that occurs every 16 words. For instance, if the device is read from 000011h, 000013h, ... ,00001Fh (odd), one wait state is inserted before the data of 000020h is output. This wait is inserted only at the boundary of the first 16 words. Then, if the device is read from the odd address within the last 16 words of 64 word boundary (address 000031h,000033h, ... , 00003Fh), a three-cycle latency occurs before data appears for the next address (address 000040h). During the boundary crossing condition, the system must assert an additional wait state for WS128J model numbers 10 and 11. The RDY output indicates this condition to the system by pulsing deactive (low). See Figure 35, "Latency with Boundary Crossing," on page 89. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, "Device Bus Operations," on page 14. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above in the subsequent bank. If the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 2.)
Table 2.
Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words
Burst Address Groups
Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,...
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As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 or 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus.
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active.
Handshaking
The device is equipped with a handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the active edge of RDY after OE# goes low. For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See "Set Configuration Register Command Sequence" section on page 47 for more information.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 38, "Back-toBack Read/Write Cycle Timings," on page 92 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-whileprogram and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read mode, it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 17, "Configuration Register," on page 51). The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four.
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An erase operation can erase one sector, multiple sectors, or the entire device. Table 12, "WS128J Sector Address Table," on page 33 and Table 13, "WS064J Sector Address Table," on page 41 indicate the address space that each sector occupies. The device address space is divided into four banks. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in the "DC Characteristics" section on page 70 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (which is separate from the memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 3, "Autoselect Codes (High Voltage Method)," on page 18. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table , "," on page 18 and Table , "," on page 21). Table 3 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15- DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 18, "Command Definitions," on page 60. Note that if a Bank Address (BA) on address bits A22, A21, and A20 for the WS128J (A21:A19 for the WS064J) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 18, "Command Definitions," on page 60. This method does not require VID. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the "Autoselect Command Sequence" section on page 51 for more information.
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Table 3.
Description Manufacturer ID: Spansion Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification L L H H L L H H CE# L OE# L WE# H
Autoselect Codes (High Voltage Method)
Amax to A12 X A11 to A10 X A9 VID A8 X A7 X A6 L A5 to A4 X A3 L L X X VID X L L L H H SA X VID X L L L L A2 L L H H L A1 L L H H H A0 L H L H L DQ15 to DQ0 0001h 227Eh 2218h (WS128J) 221Eh (WS064J) 2200h (WS128J) 2201h (WS064J) 0001h (protected), 0000h (unprotected) DQ15 - DQ8 = 0 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 = Handshake Bit 1 = Reserved, 0 = Standard Handshake DQ4 & DQ3 - Boot Code DQ2 - DQ0 = 001 0001h (protected), 0000h (unprotected)
RESET# H
Indicator Bits
L
L
H
H
X
X
VID
X
X
L
X
L
L
H
H
Hardware Sector Group Protection
L
L
H
H
SA
X
VID
X
X
X
L
L
L
H
L
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Notes: 1. The autoselect codes may also be accessed in-system via command sequences. 2. PPB Protection Status is shown on the data bus
Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both programming and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table , "," on page 18 and Table , "," on page 21).)
Table 4.
S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 3)
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX, 00000010XXX, 00000011XXX, Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords
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Table 4.
S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 3)
Sector SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151-SA154 SA155-SA158 SA159-SA162 SA163-SA166 A22-A12 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
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Table 4.
S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 3 of 3)
Sector SA167-SA170 SA171-SA174 SA175-SA178 SA179-SA182 SA183-SA186 SA187-SA190 SA191-SA194 SA195-SA198 SA199-SA202 SA203-SA206 SA207-SA210 SA211-SA214 SA215-SA218 SA219-SA222 SA223-SA226 SA227-SA230 SA231-SA234 SA235-SA238 SA239-SA242 SA243-SA246 SA247-SA250 SA251-SA254 SA255-SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 A22-A12 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
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Table 5.
S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 2)
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
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Table 5.
S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 2)
Sector SA123-SA126 SA127-SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 A21-A12 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
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Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = VIL (All sectors locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
(All boot sectors locked)
WP# = VIL
64-bit Password
(One Time Protect)
PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked
1. Bit is volatile, and defaults to "1" on reset. 2. Programming to "0" locks all PPBs to their current state. 3. Once programmed to "0", requires hardware reset to unlock.
Memory Array
Sector 0 Sector 1 Sector 2
Persistent Protection Bit (PPB)4,5
PPB 0 PPB 1 PPB 2
Dynamic Protection Bit (PPB)6,7,8
DYB 0 DYB 1 DYB 2
Sector N-2 Sector N-1 Sector N
3
PPB N-2 PPB N-1 PPB N
4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively
DYB N-2 DYB N-1 DYB N
6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is "1" (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options).
3. N = Highest Address Sector.
Figure 1.
Advanced Sector Protection/Unprotection
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Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device programmer or host system must then choose which sector protection method to use. Programming (setting to "0") any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit (DQ1) Lock Register Password Protection Mode Lock Bit (DQ2)
Table 6.
Device S29WS256N DQ15-05 1 DQ4 1 DYB Lock Boot Bit 0 = sectors power up protected 1 = sectors power up unprotected
Lock Register
DQ3 1 DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Customer SecSi Sector Protection Bit
S29WS128N/ S29WS064N
Undefined
PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled
Password Protection Mode Lock Bit
Persistent Protection Mode Lock Bit
SecSi Sector Protection Bit
Notes 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: 1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections -.
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. Notes 1. Each PPB is individually programmed and all are erased in parallel. 2. While programming PPB for a sector, array data can be read from any other bank, except Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed. 3. Entry command disables reads and writes for the bank selected. 4. Reads within that bank return the PPB status for that sector. 5. Reads from other banks are allowed while writes are not allowed.
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6. All Reads must be performed using the Asynchronous mode. 7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are written at the same time as the program command. 8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB. 9. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 10.Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11.The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 2.
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Enter PPB Command Set. Addr = BA
Program PPB Bit. Addr = SA
Read Byte Twice Addr = SA0
DQ6 = Toggle? Yes No
No
DQ5 = 1? Yes Read Byte Twice Addr = SA0 Wait 500 s
DQ6 = Toggle? Yes
No
Read Byte. Addr = SA
No
DQ0 = '1' (Erase) '0' (Pgm.)? Yes
FAIL
Issue Reset Command
PASS
Exit PPB Command Set
Figure 2.
PPB Program/Erase Algorithm
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to "1"). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
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Notes 1. The DYBs can be set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectorsmay be modified depending upon the PPB state of that sector (see Table 7). 3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to "0"). 4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to "0"), it locks all PPBs and when cleared (programmed to "1"), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set (programmed to "0") only after all PPBs are configured to the desired settings.
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set "0" to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. 2. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out with the cell as a "0". 3. The password is all "1"s when shipped from the factory. 4. All 64-bit password combinations are valid as a password. 5. There is no means to verify what the password is after it is set. 6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. The Password Mode Lock Bit is not erasable. 8. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. 9. The exact password must be entered in order for the unlocking function to occur.
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10.The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11.Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12.Password verification is only allowed during the password programming operation. 13.All further commands to the password region are disabled and all operations are ignored. 14.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15.Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16.If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17.A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Write Enter Lock Register Command: Address 555h, Data 40h
Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD
XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once.
Wait 4 s
Perform Polling Algorithm
(see Write Operation Status flowchart)
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
FAIL. Write rest command to return to reading array.
Figure 3.
Lock Register Program Algorithm
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Advanced Sector Protection Software Examples
Table 7.
Unique Device PPB Lock Bit 0 = locked 1 = unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1
Sector Protection Schemes
Sector PPB 0 = protected 1 = unprotected 0 0 1 1 0 0 1 1 Sector DYB 0 = protected 1 = unprotected x x 1 0 x x 0 1 Sector Protection Status Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected
Table 7 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to "0"), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to "1") through a hardware reset or power cycle. See also Figure 1 for an overview of the Advanced Sector Protection feature.
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the "outermost" boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are disabled and hence all sectors are protected.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch Protection"
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to the autoselect mode.
Table 8.
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 9.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0003h 0000h 0009h 0000h 0004h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10.
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h (WS128J) 0017h (WS064J) 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh (WS128J) 007Dh (WS064J) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Table 11.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0011 = 0.13 m Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation Number of Sectors in all banks except boot block Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization: X = Number of banks Bank A Region Information. X = Number of sectors in bank Bank B Region Information. X = Number of sectors in bank Bank C Region Information. X = Number of sectors in bank Bank D Region Information. X = Number of sectors in bank
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh
0002h 0001h 0001h 0007h 00E7h (WS128J) 0077h (WS064J) 0001h 0000h 00B5h 00C5h 0001h 0000h 0004h 0027h (WS128J) 0017h (WS064J) 0060h (WS128J) 0030h (WS064J) 0060h (WS128J) 0030h (WS064J) 0027h (WS128J) 0017h (WS064J)
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Table 12.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank D SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
WS128J Sector Address Table (Sheet 1 of 8)
Sector Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
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Table 12.
Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 Bank C SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
WS128J Sector Address Table (Sheet 2 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
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Table 12.
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 Bank C SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102
WS128J Sector Address Table (Sheet 3 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh
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Table 12.
Bank Sector SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 Bank C SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
WS128J Sector Address Table (Sheet 4 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh
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Table 12.
Bank Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 Bank B SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166
WS128J Sector Address Table (Sheet 5 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh 4B8000h-4BFFFFh 4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh
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Table 12.
Bank Sector SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 Bank B SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
WS128J Sector Address Table (Sheet 6 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-55FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh 5F8000h-5FFFFFh
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Table 12.
Bank Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank B SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
WS128J Sector Address Table (Sheet 7 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh
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Table 12.
Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 Bank A SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
WS128J Sector Address Table (Sheet 8 of 8)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords (x16) Address Range 700000h-707FFFh 708000h-70FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh 7F9000h-7F9FFFh 7FA000h-7FAFFFh 7FB000h-7FBFFFh 7FC000h-7FCFFFh 7FD000h-7FDFFFh 7FE000h-7FEFFFh 7FF000h-7FFFFFh
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Table 13.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank D SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
WS064J Sector Address Table (Sheet 1 of 6)
Sector Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh
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Table 13.
Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 Bank C SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46
WS064J Sector Address Table (Sheet 2 of 6)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh
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Table 13.
Bank Sector SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank C SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
WS064J Sector Address Table (Sheet 3 of 6)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
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Table 13.
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 Bank B SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94
WS064J Sector Address Table (Sheet 4 of 6)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh
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Table 13.
Bank Sector SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 Bank B SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
WS064J Sector Address Table (Sheet 5 of 6)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
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Table 13.
Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank A SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
WS064J Sector Address Table (Sheet 6 of 6)
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords (x16) Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 18, "Command Definitions," on page 60 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erasesuspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See the "Erase Suspend/Erase Resume Commands" section on page 55 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the "Reset Command" section on page 51 for more information.
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See also "Requirements for Asynchronous ReadOperation (Non-Burst)" section on page 14 and "Requirements for Synchronous (Burst) Read Operation" section on page 14 for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 15, "CLK Synchronous Burst Mode Read (rising active CLK)," on page 74, Figure 17, "Synchronous Burst Mode Read," on page 75, and Figure 20, "Asynchronous Mode Read with Latched Addresses," on page 77 show the timings.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11-A0 should be 555h, and address bits A19-A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock).
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Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (A19 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (A19 = 1)
Synchronous Read Mode Only
Figure 4. Read Mode Setting
Synchronous/Asynchronous State Diagram
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: "1" for asynchronous mode, "0" for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting (see Table 14, "Programmable Wait State Settings," on page 49). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency.
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Table 14.
A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1
Programmable Wait State Settings
A12 0 1 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 (default) Reserved Reserved
Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting.
Standard wait-state Handshaking Option
The host system must set the appropriate number of wait states in the flash device depending upon the clock frequency. The host system should set address bits A14-A12 to 010 for a clock frequency of 66/80 MHz for the system/device to execute at maximum speed. Table 15 describes the recommended number of clock cycles (wait states) for various conditions.
Table 15.
Wait States for Standard wait-state Handshaking
Typical No. of Clock Cycles after AVD# Low
Burst Mode 8-Word or 16-Word or Continuous 32-Word
66 MHz 4 5
80 MHz 6 or 7 7
Notes: 1. In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). 2. For WS128J model numbers 10 and 11, an additional clock cycle is required for boundary crossings while in Continuous read mode.
The host system must set the appropriate number of wait states in the flash device depending upon the clock frequency. Note that the host system must set again the number of wait state when the host system change the clock frequency. For example, the host system must set from 6 or 7 wait state to less than 5 wait states when the host system change the clock frequency from 80MHz to less than 80MHz. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See the "Autoselect Command Sequence" section on page 51 for more information.
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Read Mode Configuration
The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eightword mode. Table 16 shows the address bits and settings for the four read modes.
Table 16.
Read Mode Settings
Address Bits
Burst Modes Continuous 8-word linear wrap around 16-word linear wrap around 32-word linear wrap around
A16 0 0 1 1
A15 0 1 0 1
Note: Upon power-up or hardware reset the default setting is continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. Address bit A17 determines this setting; "1" for rising active, "0" for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; "1" for RDY active with data, "0" for RDY active one clock cycle before valid data. Only the combination of wait state 2 and RDY active one clock cycle before data is not supported. In asynchronous mode, RDY is an open-drain output.
Configuration Register
Table 17 shows the address bits that determine the configuration register settings for various device functions.
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Table 17.
Address Bit A19 A18 A17 A16 A15 A14 A13 Read Mode Function Set Device Read Mode RDY Clock Settings (Binary)
Configuration Register
0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) Synchronous Mode 00 01 10 11 = Continuous (default) = 8-word linear with wrap around = 16-word linear with wrap around = 32-word linear with wrap around Data Data Data Data Data Data is is is is is is valid valid valid valid valid valid on on on on on on the the the the the the 2nd active CLK edge after AVD# transition to VIH 3rd active CLK edge after AVD# transition to VIH 4th active CLK edge after AVD# transition to VIH 5th active CLK edge after AVD# transition to VIH 6th active CLK edge after AVD# transition to VIH 7th active CLK edge after AVD# transition to VIH (default)
A12
000 = 001 = 010 = Programmable 011 = 100 = Wait State 101 =
110 = Reserved 111 = Reserved
Note: Device is in the default state upon power-up or hardware reset.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 18, "Command Definitions," on page 60 shows the address and data requirements. The autoselect command sequence may be
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written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and SA represents the sector address. The device ID is read in three cycles. Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Sector Protection Verification Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh (SA) + 02h Read Data 0001h 227Eh 2218h (WS128J) 221Eh (WS064J) 2200h (WS128J) 2201h (WS064J) 0001 (locked), 0000 (unlocked) DQ15 - DQ8 = 0 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 - Handshake Bit Indicator Bits (BA) + 03h 1 = Reserved, 0 = Standard Handshake DQ4 & DQ3 - Boot Code 00 = Dual Boot Sector, 01 = Top Boot Sector, 10 = Bottom Boot Sector DQ2 - DQ0 = 001 The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 18, "Command Definitions," on page 60 shows the address and data requirements for both command sequences.
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The following commands are not allowed when the Secured Silicon is accessible. CFI Unlock Bypass Entry Unlock Bypass Program Unlock Bypass Reset Erase Suspend/Resume Chip Erase
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 18, "Command Definitions," on page 60 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the "Write Operation Status" section on page 62 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to a array faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 18, "Command Definitions," on page 60 shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The array then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to accelerate the operation.
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Figure 5, "Program Operation," on page 54 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 23, "Asynchronous Program Operation Timings: AVD# Latched Addresses," on page 81 and Figure 25, "Synchronous Program Operation Timings: WE# Latched Addresses," on page 83 for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 18 for program command sequence.
Figure 5.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 18, "Command Definitions," on page 60 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the "Write Operation Status" section on page 62 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
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The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles. See Table 18, "Command Definitions," on page 60 for details on the unlock bypass command sequences. Figure 6, "Erase Operation," on page 56 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 18, "Command Definitions," on page 60 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal operation will not be guaranteed. The system can monitor DQ3 to determine if the sector erase timer has timed out (See "DQ3: Sector Erase Timer" section on page 67.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the "Write Operation Status" section on page 62 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 6, "Erase Operation," on page 56 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics on page 72 for parameters and timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase op-
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eration, including the minimum 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , "Write Operation Status," on page 62 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspendread mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the "Write Operation Status" section on page 62 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the "Autoselect Mode" section on page 17 and "Autoselect Command Sequence" section on page 51 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 18 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer
Figure 6.
Erase Operation
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Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status except DQ7. Once programming is complete, the user must issue a Read/Reset command to the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a timeout by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Secured Silicon Exit command returns the device back to normal operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed, the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection Mode. After issuing "PL/68h" at the fourth bus cycle, the device requires a time out period of approximately 150 s for programming the Password Protection Mode Locking Bit. Then by writing "PL/48h" at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of "PL/68h". Exiting the Password Protection Mode Locking Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. After issuing "SL/68h" at the fourth bus cycle, the device requires a time out period of approximately 150 s for programming the Persistent Protect ion Mode Locking Bit. Then by writ ing "SMPL/48h" at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Persistent Protection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of "PL/68h". Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or Read/Reset command.
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Secured Silicon Sector Protection Bit Program Command
To protect the Secured Silicon Sector, write the Secured Silicon Sector Protect command sequence while in the Secured Silicon Sector mode. After issuing "OW/48h" at the fourth bus cycle, the device requires a time out period of approximately 150 s to protect the Secured Silicon Sector. Then, by writing "OPBP/48" at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Secured Silicon Sector is protected. If not, then the system must repeat this program sequence from the fourth cycle of "OPBP/48h". Exiting the Secured Silicon Sector Protection Mode Locking Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or Read/Reset command.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Secured Silicon Exit command, only while in the Persistent Sector Protection Mode.
DPB Write/Erase/Status Command
The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (Amax-A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. If the PPB is set, the sector is protected regardless of the value of the DPB. If the PPB is cleared, setting the DPB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DPBs. The programming of the DPB for a given sector can be verified by writing a DPB Status command to the device. Exiting the DPB Write/Erase command is accomplished by writing the Read/Reset command. Exiting the DPB Status command is accomplished by writting the Secured Silicon Sector Exit command
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock command is not address order specific. The lower address A1-A0= 00, the next Password Unlock command is to A1-A0= 01, then to A1-A0= 10, and finally to A1-A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Also, reading the Bank D results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the other bank returns actual array data. Approximately 1s is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. Four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep
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track of the number of Password Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. Exiting the Password Unlock command is accomplished by writing the Secured Silicon Sector Exit command.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (Amax-A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. After 4th cycle, the device requires approximately 150 s time out period for programming the PPB. And then after 5th cycle, the device outputs verify data at DQ0. The PPB Program command does not follow the Embedded Program algorithm. Writing the Secured Silicon Sector Exit command or Read/Reset command return the device back to normal operation.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will timeout without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. After 4th cycle, the device requires approximately 1.5 ms time out period for erasing the PPB. And then after 5th cycle, the device outputs verify data at DQ0. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the Secured Silicon Sector Exit command or Read/Reset command return the device back to normal operation.
PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. Writing the Secured Silicon Sector Exit command or Read/Reset command return the device back to normal operation.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Writing the Secured Silicon Sector Exit command or Read/ Reset command return the device back to normal operation.
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Command Definitions
Table 18.
Command Sequence (Note 1) Asynchronous Read (Note 7) Reset (Note 8) Autoselect (Note 9) Manufacturer ID Device ID (Note 10) Sector Lock Verify (Note 11) Indicator Bits Cycles First Addr RA XXX 555 555 555 555 555 555 555 BA BA 555 55 Data RD F0 AA AA AA AA AA AA AA B0 30 AA 98 2AA 55 (CR) 555 C0 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 (BA) 555 (BA) 555 (SA) 555 (BA) 555 555 555 555 90 90 90 90 A0 80 80 (BA) X00 (BA) X01 (SA) X02 (BA) X03 PA 555 555 0001 227E 0000/ 0001 (Note 12) Data AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X (Note 0E 10) (BA) X0F (Not e 10)
Command Definitions
Bus Cycles (Notes 1-6) Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data
Second Addr Data
1 1 4 6 4 4 4 6 6 1 1 3 1
Program Chip Erase Sector Erase Erase Suspend (Note 15) Erase Resume (Note 16) Set Configuration Register (Note 17) CFI Query (Note 18)
Unlock Bypass Entry Unlock Bypass Program (Notes 13, 14) Unlock Bypass Mode Unlock Bypass Sector Erase (Notes 13, 14) Unlock Bypass Erase (Notes 13, 14) Unlock Bypass Reset (Notes 13, 14)
3 2
555 XX
AA A0
2AA PA
55 PD
555
20
2 2 2
XX XX XX
80 80 90
SA XXX XXX
30 10 00
Sector Protection Command Definitions Secured Silicon Sector Entry Secured Silicon Sector Secured Silicon Sector Exit Secured Silicon Protection Bit Program (Notes 19, 21) 3 4 555 555 AA AA 2AA 2AA 55 55 555 555 88 90 XX 00 RD (0)
6
555
AA
2AA
55
555
60
OW XX0
68 PD0 PD1 PD2 PD3 PD0 PD1 PD2 PD3 PD0
OW
48
OW
Password Program (Notes 23)
4
555
AA
2AA
55
555
38
XX1 XX2 XX3 XX0
Password Protection Password Verify 4 555 AA 2AA 55 555 C8
XX1 XX2 XX3
Password Unlock (Note 23)
7
555
AA
2AA
55
555
28
XX0
XX1
PD1
XX2
PD2
XX3
PD3
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Command Sequence (Note 1)
Cycles
Bus Cycles (Notes 1-6) First Addr Data Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data
PPB Program (Notes 21) PPB All PPB Erase (Notes Commands 22, 24) PPB Status (Note 25) PPB Lock Bit PPB Lock Bit Set PPB Lock Bit Status DPB Write DPB DPB Erase DPB Status Password Protection Mode Locking Bit Program (Notes 21) Persistent Protection Mode Locking Bit Program (Notes 21) Legend:
6 6 4 3 4 4 4 4 6 6
555 555 555 555 555 555 555 555 555 555
AA AA AA AA AA AA AA AA AA AA
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55 55 55 55 55
555 555 SBA 555 555 (BA) 555 555 555 (BA) 555 555 555
60 60 90 78 58 48 48 58 60 60
SBA + WP WPE SBA +WP
68 60 RD (0) RD (1) X1 X0 RD (0) 68 68
SBA + WP SBA WPE
48 40
XX XX
RD (0) RD (0)
BA SA SA SA PL SL
PL SL
48 48
PL SL
RD (0) RD (0)
X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax-A12 uniquely select any sector. BA = Address of the bank (WS128J: A22, A21, A20, WS064J: A21, A20, A19) that is being switched to autoselect mode, is in bypass mode, or is being erased. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. SBA = sector address block to be protected. CR = Configuration Register address bits A19-A12. OW = Address (A7-A0) is (00011010). PD3-PD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. PL = Address (A7-A0) is (00001010) RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SL = Address (A7-A0) is (00010010) WD= Write Data. See "Configuration Register" definition for specific write data WP = Address (A7-A0) is (00000010) WPE = address(A7-A0) is (01000010)
Notes: 1. See Table 1 for description of bus operations.
2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. All values are in hexadecimal. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0. Unless otherwise noted, address bits Amax-A12 are don't cares. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. (BA)X0Fh = 2200h (WS128J), (BA)X0Eh = 2218h (WS128J), (BA)X0Fh = 221Eh (WS064J), (BA)X0Eh = 2201h (WS064J) The data is 0000h for an unlocked sector and 0001h for a locked sector DQ15 - DQ8 = 0, DQ7 - Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6 -Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5 = Handshake Bit (1 = Reserved, 0 = Standard Handshake)8, DQ4 & DQ3 - Boot Code (00= Dual Boot Sector, 01= Top Boot Sector, 10= Bottom Boot Sector, 11=No Boot Sector), DQ2 - DQ0 = 001 The Unlock Bypass command sequence is required prior to this command sequence.
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14. The Unlock Bypass Reset command is required to return to reading array data. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 17. See "Set Configuration Register Command Sequence" for details.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
19. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous read operations. 20. ACC must be at VHH during the entire operation of this command 21. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 22. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 23. The entire four bus-cycle sequence must be entered for each portion of the password. 24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 20, "Write Operation Status," on page 67 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles. Table 20, "Write Operation Status," on page 67 shows the outputs for Data# Polling on DQ7. Figure 7, "Data# Polling Algorithm," on page 63 shows the Data# Polling algorithm. Figure 29, "Data# Polling Timings (During Embedded Algorithm)," on page 86 in the AC Characteristics section shows the Data# Polling timing diagram.
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START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 7.
Data# Polling Algorithm
RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence.
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 20, "Write Operation Status," on page 67 shows the outputs for RDY.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase timeout. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 8, "Toggle Bit Algorithm," on page 65, DQ6: Toggle Bit I on page 64, Figure 30, "Toggle Bit Timings (During Embedded Algorithm)," on page 87 (toggle bit timing diagram), and Table 19, "DQ6 and DQ2 Indications," on page 66. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserteed and reasserted to show the change in state.
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START
Read Byte (DQ0-DQ7) Address = VA Read Byte (DQ0-DQ7) Address = VA
DQ6 = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA
DQ6 = Toggle?
No
Yes FAIL PASS
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 8.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
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Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 19, "DQ6 and DQ2 Indications," on page 66 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 8, "Toggle Bit Algorithm," on page 65, See DQ6: Toggle Bit I on page 64, Figure 30, "Toggle Bit Timings (During Embedded Algorithm)," on page 87, and Table 19, "DQ6 and DQ2 Indications," on page 66.
Table 19.
If device is programming, and the system reads at any address,
DQ6 and DQ2 Indications
then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable.
actively erasing,
at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at any address,
erase suspended,
programming in erase suspend
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8, "Toggle Bit Algorithm," on page 65 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (Figure 8, "Toggle Bit Algorithm," on page 65).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed.
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The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also Sector Erase Command Sequence on page 55. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 20 shows the status of DQ3 relative to the other status bits.
Table 20.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspended Sector Non-Erase Suspended Sector
Write Operation Status
DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle (Note 6) Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle (Note 6) Toggle Toggle Data N/A RDY (Note 5) 0 0 High Impedance High Impedance 0
Standard Mode
Erase Suspend Mode
Erase-SuspendRead (Note 4)
Erase-Suspend-Program
Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchronously (burst) while in erase suspend. 5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This is available in the Asynchronous mode only. 6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.
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Sheet
Absolute Maximum Ratings
Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +2.5 V A9, RESET#, ACC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 10. 2. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
Figure 9.
Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns
Figure 10.
Maximum Positive Overshoot Waveform
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Data
Sheet
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Industrial (I) Devices Supply Voltages
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 V to 1.95 V (66MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.70 V to 1.95 V (80MHz)
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
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Data
Sheet
DC Characteristics
CMOS Compatible
Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions Notes: 1 VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous IIO1 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VOL VOH VID VHH VLKO VCC Non-active Output VCC Active Asynchronous Read Current (Note 2) VCC Active Write Current (Note 3) VCC Standby Current (Note 4) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (Note 5) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Autoselect and Temporary Sector Unprotect Voltage for Accelerated Program Low VCC Lock-out Voltage IOL = 100 A, VCC = VCC min = VIO IOH = -100 A, VCC = VCC min VCC = 1.8 V VCC - 0.1 11.5 11.5 1.0 12.5 12.5 1.4 OE# = VIH 10 MHz CE# = VIL, OE# = VIH, WE# = VIH 5 MHz 1 MHz 66 MHz 80 MHz 66 MHz 80 MHz 66 MHz 80 MHz 15 18 15 18 15 18 0.2 20 12 3.5 15 0.2 0.2 66 MHz 80 MHz 22 25 0.2 VACC VCC -0.5 VCC - 0.4 7 5 Min Typ Max 1 1 30 36 30 36 30 36 10 30 16 5 40 50 50 54 60 50 15 10 0.4 VCC + 0.4 0.1 V V V V V Unit A A mA mA mA mA mA mA A mA mA mA mA A A mA mA A mA mA V
CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 12.0 0.5 V
Notes: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 5. Total current during accelerated programming is the sum of VACC and VCC currents. 6. 80 MHz applies only to the WS064J.
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Data
Sheet
Test Conditions
Device Under Test CL
Figure 11. Table 21.
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Setup
Test Specifications
All Speed Options 30 2.5 - 3 0.0-VCC VCC/2 VCC/2 Unit pF ns V V V
Key to Switching Waveforms
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs
Switching Waveforms
All Inputs and Outputs VCC 0.0 V Input VCC/2 Measurement Level VCC/2 Output
Figure 12.
Input Waveforms and Measurement Levels
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Data
Sheet
AC Characteristics
VCC Power-up
Parameter tVCS tRSTH
Notes:
1. VCC ramp rate is > 1V / 100s 2. VCC ramp rate <1V / 100s, a Hardware Reset will be required.
Description VCC Setup Time RESET# Low Hold Time
Test Setup Min Min
Speed 50 50
Unit s s
tVCS VCC
RESET#
Figure 13.
VCC Power-up Diagram
CLK Characterization
Parameter Description Max Min fCLK CLK Frequency Min 32.0 32.0 KHz 66 MHz 66.0 15.2 80 MHz (WaitState=6,7) 80.0 66.0 80 MHz (WaitState less than 5) 66.0 18.2 Unit MHz MHz continuous burst , CLK duty 50% +/10% 8/16/32-word burst, CLK duty 50% +/10% continuous burst 8/16/32-word burst Condition
Min tCLKH tCLKL tCR tCF CLK high time CLK Low Time CLK Rise Time CLK Fall Time Min Min Max
39.6 7 7.0 3
5 5.0 2.5
33.0 5 5.0 2.5
ns ns ns ns
Note: 80 MHz applies only to the WS064J.
tCLK tCH tCL
CLK
tCR
tCF
Note: For WS128J (model numbers 10 and 11), and additional clock cycle is required during boundary crossing while in continuous read mode.
Figure 14. 72
CLK Characterization S29WS-J_00_A6 May 11, 2006
S29WS128J/064J
Data
Sheet
Synchronous/Burst Read
Parameter Description JEDEC Standard tIACC tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD tACC tCKA tCKZ tOES Latency (Standard wait-state Handshake mode) for 8-Word and and Continuous 16-Word Burst Latency (Standard wait-state Handshake mode) for 32-Word Burst Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note 1) Address Hold Time to AVD# (Note 1) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Access Time CLK to access resume CLK to High Z Output Enable Setup Time Max Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min Min Max Max Max Min 55 11.2 8 4 11.2 4 5.5 0 4 10 55 9.1 11.2 11.2 8 8 4 4 9.1 56 71 11.2 4 5.5 2 9.1 9.1 66 MHz 80 MHz (WS064J only) 71 84 9.1 Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
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Data
Sheet
CE# CLK tAVC AVD# tACS Addresses
Aa
tCES 1 2 3
7 cycles for initial access shown.
tCEZ 6 7
4
5
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
Da + n
tOEZ tRACC
Hi-Z
tOE
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or three additional clock cycle when wait state is set to 6 & 7 are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 15.
CLK Synchronous Burst Mode Read (rising active CLK)
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Data
Sheet
CE# CLK tAVC AVD# tACS Addresses
Aa
tCES 1
4 cycles for initial access shown.
tCEZ 5
2
3
4
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE#
Hi-Z Da
Da + 1
Da + n
tOEZ tRACC
Hi-Z
tCR
tOE
RDY tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or three additional clock cycle when wait state is set to 6 & 7 are inserted, clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 16.
tCAS CE# 1 CLK tAVC AVD# tAAS Addresses
Aa
CLK Synchronous Burst Mode Read (Falling Active Clock)
7 cycles for initial access shown.
tCEZ 5 6 7
2
3
4
tAVD
tAAH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
tBACC
Hi-Z Da + n
tBDH tRACC
tOEZ
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 17.
Synchronous Burst Mode Read
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Data
Sheet
tCES CE# 1 CLK tAVC AVD# tACS Addresses
AC
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH
tOE
tRACC
tRACC
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode with wrap around. 4. D0-D7 in data waveform indicates the order the data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (AC)
Figure 18.
8-word Linear Burst with Wrap Around
tCEZ 6
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
6 wait cycles for initial access shown.
2
3
4
5
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z Da Da+1
tBACC
Hi-Z Da+2 Da+3 Da + n
tRACC tOE
tBDH
tOEZ
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data.
Figure 19.
Linear Burst with RDY Set One Cycle Before Data
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Data
Sheet
Asynchronous Mode Read
Parameter Description JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS 66 MHz Max Max Min Min Min Max Min Min Max Min 11.2 0 8 8 0 55 55 10 4 5.5 9.1 80 MHz (WS064J only) 55 55 Unit ns ns ns ns ns ns ns ns ns ns
Access Time from CE# Low
Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Output Enable Hold Time Output Enable to High Z CE# Setup Time to AVD# Read Toggle and Data# Polling
CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS RA tAAVDH tCE Valid RD tOEZ
OE#
Note: RA = Read Address, RD = Read Data.
Figure 20.
Asynchronous Mode Read with Latched Addresses
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Data
Sheet
CE# tOE tOEH WE# Data tACC Addresses RA tCE Valid RD tOEZ
OE#
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 21.
Asynchronous Mode Read
Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode All Speed Options Unit
Max Max Min Min Min
35 500 500 200 20
s ns ns ns s
Note: Not 100% tested.
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Data
Sheet
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CE#, OE# tReady RESET# tRP
Figure 22.
Reset Timings
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Data
Sheet
Erase/Program Operations
Parameter Description JEDEC tAVAV tAVWL Standard tWC tAS Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Synchronous Asynchronous Synchronous Asynchronous Min Min 66 MHz 80 MHz (WS064J only) 45 4 0 5.5 20 10 20 0 0 0 0 20 20 0 <7 <4 <0.2 <104 500 1 50 0 4 4 4 5 Unit ns ns
tWLAX
tAH tAVDP
Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High
Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min Min Min Min Min Min
ns ns ns ns ns ns ns ns ns ns s s sec ns s s ns ns ns ns ns
tDVWH tWHDX tGHWL
tDS tDH tGHWL tCAS
tWHEH tWLWH tWHWL
tCH tWP tWPH tSR/W
Latency Between Read and Write Operations Programming Operation (Note 4) Accelerated Programming Operation (Note 4) Sector Erase Operation (Notes 4, 5) Chip Erase Operation (Notes 4, 5) VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Hold Time to CLK Clock Setup Time to WE#
tWHWH1 tWHWH1 tWHWH2
tWHWH1 tWHWH1 tWHWH2 tVID tVIDS tVCS
tELWL
tCS tAVSW tAVHW tAVHC tCSW
Notes: 1. Not 100% tested. 2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program operation timing, addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 4. See the Erase and Programming Performance section for more information. 5. Does not include the preprogramming time.
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Data
Sheet
VIH
Program Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 555h tAH PA VA
In Progress
VA
Data
A0h
PD tDS tDH
Complete
CE#
OE# tWP WE# tCS
tCH
tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A22-A12 are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 23.
Asynchronous Program Operation Timings: AVD# Latched Addresses
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Data
Sheet
Program Command Sequence (last two cycles) CLK tACS tCSW AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE# tAVSW
A0h
PD tDS tDH
Complete
OE#
tAH tWP
tCH
WE#
tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A22-A12 are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 24.
Asynchronous Program Operation Timings: WE# Latched Addresses
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Data
Sheet
Program Command Sequence (last two cycles) tAVCH CLK tACS tCSW AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE# tAVSW
A0h
PD tDS tDH
Complete
OE#
tAH tWP
tCH
WE#
tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A22-A12 are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 25.
Synchronous Program Operation Timings: WE# Latched Addresses
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Data
Sheet
Program Command Sequence (last two cycles) tAVCH CLK tAS tAH AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWC tWPH
tVCS VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A22-A12 are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 26.
Synchronous Program Operation Timings: CLK Latched Addresses
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Data
Sheet
VIH
Erase Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
Notes:
tCH
tWHWH2 tWPH tWC
1. SA is the sector address for Sector Erase. 2. Address bits A22-A12 are don't cares during unlock cycles in the command sequence.
Figure 27.
Chip/Sector Erase Command Sequence
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Data
Sheet
CE#
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
1 s
tVIDS tVID
Note: Use setup and hold times from conventional program operation.
VIL or VIH
Figure 28.
Accelerated Unlock Bypass Programming Timing
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Notes:
Status Data
Status Data
1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 29.
Data# Polling Timings (During Embedded Algorithm)
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Data
Sheet
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Notes:
Status Data
Status Data
1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 30.
Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes:
1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
Figure 31.
Synchronous Data Polling Timings/Toggle Bit Timings
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Data
Sheet
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program
Erase Resume Erase Erase Complete
Erase Suspend Read
Erase Erase Suspend Suspend Read Program
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 32.
DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RDY High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s
Note: Not 100% tested.
VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID
VIL or VIH
WE# tRSP RDY tRRB
Figure 33.
Temporary Sector Unprotect Timing Diagram
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Data
Sheet
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid* Verify 40h
Sector Protect: 150 s Sector Unprotect: 1.5 ms
Valid*
Data 1 s CE#
60h
60h
Status
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 34.
Sector/Sector Block Protect and Unprotect Timing Diagram
Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C63 3F
C64 40
C65 41
C66 42
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
D63
D64
D65
D66
Notes:
OE#, CE#f
(stays low)
1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. 4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at the boundary crossing.
Figure 35. May 11, 2006 S29WS-J_00_A6
Latency with Boundary Crossing 89
S29WS128J/064J
Data
Sheet
Address boundary occurs every 64 words, beginning at address 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C63 3F
C64 40
C65 41
C66 42
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
D63
Invalid
Read Status
OE#, CE#
Notes:
(stays low)
1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program.
Figure 36.
Latency with Boundary Crossing into Program/Erase Bank
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Data
Sheet
Data
D0
D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD# falling edge
OE# 1 CLK 0 1 2 3
4
5
6
7
2
3
4
5
number of clock cycles programmed
Wait State Decoding Addresses:
A14, A13, A12 = "111" Reserved A14, A13, A12 = "110" Reserved A14, A14, A14, A14, A14, A14, A13, A13, A13, A13, A13, A13, A12 A12 A12 A12 A12 A12 = = = = = = "101" "100" "011" "010" "001" "000" 5 programmed, 7 total 4 programmed, 6 total 3 programmed, 5 total 2 programmed, 4 total 1 programmed, 3 total 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to "101".
Figure 37.
Example of Wait States Insertion
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Data
Sheet
Last Cycle in Program or Sector Erase Command Sequence
Read status (at least two cycles) in same bank and/or array data from other bank
Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS tDH Data
PD/30h RD
tGHWL
tACC
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information.
Figure 38.
Back-to-Back Read/Write Cycle Timings
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Sheet
Erase and Programming Performance
Parameter Sector Erase Time 32 Kword 4 Kword 128J 064J Typ (Note 1) <0.4 <0.2 <103 <53 <6 <4 <50.4 <25.2 <33 <17 <100 <67 Max (Note 2) <2 <2 Unit s Excludes 00h programming prior to erasure (Note 4) s s s s Excludes system level overhead (Note 5) Excludes system level overhead (Note 5) Comments
Chip Erase Time Word Programming Time
Accelerated Word Programming Time Chip Programming Time (Note 3) Accelerated Chip Programming Time
Notes:
128J 064J 128J 064J
s
1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 100K cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 18, "Command Definitions," on page 60 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
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Data
Sheet
Physical Dimensions
VBH084 - 84-ball Fine-Pitch Ball Grid Array (FBGA) 8x11.6 mm MCP Compatible Package (128Mb)
0.05 C (2X)
D
A
D1 e
10 9
e
8 7 6
7
SE E1
E
5 4 3 2 1 M L K J H G F E D C B A
A1 CORNER
A1 CORNER
INDEX MARK
B
10
0.05 C (2X)
6
SD
0.08 M C 0.15 M C A B
7
NXb
TOP VIEW
BOTTOM VIEW
A
A1
SEATING PLANE
A2
0.10 C
C
0.08 C
SIDE VIEW
NOTES: PACKAGE JEDEC VBH 084 N/A 11.60 mm x 8.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.33 MIN --0.18 0.62 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 --0.80 BSC. 0.40 BSC. (A2-A9, B10-L10, M2-M9, B1-L1) 0.43 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note: BSC is an ANSI standard for Basic Space Centering
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Data
Sheet
VBR080 - 80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm (64Mb)
0.15 C (2X)
D1 D
A
e
8
e
7 6 5
7
SE E1
E
4 3 2 1 K J H G F E D C B A
A1 CORNER
A1 CORNER
INDEX MARK
10
B
0.15 C (2X)
6
NXb
0.08 M C 0.15 M C A B
SD
7
TOP VIEW BOTTOM VIEW
A
A1
SEATING PLANE
A2
0.20 C
C
0.08 C
SIDE VIEW
NOTES: PACKAGE JEDEC VBR 080 N/A 9.00 mm x 7.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.35 MIN --0.17 0.62 NOM --- ---9.00 BSC. 7.00 BSC. 7.20 BSC. 5.60 BSC. 10 8 80 --0.80 BSC. 0.40 BSC. NONE 0.45 MAX 1.00 --0.73 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3366 \ 16-038.25d1
Note: BSC is an ANSI standard for Basic Space Centering
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Data
Sheet
Revision Summary
Revision A0 (July 22, 2004)
Initial release.
Revision A1 (October 6, 2004)
Add `BF' parts on Valid Combination table.
Revision A2 (December 10, 2004)
Remove all in terms of 104MHz speed bin. Change statement of command during time-out period of sector erase. Change exit command statement about password program command Change exit command statement about password protection mode locking bit program command Change exit command statement about persistentsector protection mode locking bit program command Change exit command statement about Secured Silicon sector protection bit program command Change exit command statement about PPB program command Change exit command statement about All PPB erase command Change exit command statement about PPB/PPB lock bit status command Change PPB command table. Remove note 19 in command table. Change waveform about boundary crossing. Remove DC spec output disable status in synchronous read mode. Change the word from SMPL to PL , from OPBP to OW. Change the statement PPB Lock Bit Set Command. Delete VIO pin Added description at "RDY Configuration" in page56 Modified tAH in Asynchronous mode to 20ns in page89
Revision A3 (February 19, 2005)
Change "Secsi" to "Secured Silicon" Add migration statement. Modify "Sync Latency", "Asyn Access time" @80MHz Update "Product Selector Guide" on tACC, tCE, tIACC@80MHz Modify Table 15( "Wait States for Standard Wait-state Handshaking") Change "Supply Voltage" to "1.70V to 1.95V for 80MHz parts Modify "CLK Characterization" table
Revision A4 (June 24, 2005)
Added information for "Revision 1" for boundary crossing while in Continuous read mode Removed all references to WS128J 80 MHz and WS064J Industrial grades
Revision A5 (March 31, 2006)
Updated the Valid Combinations table for the 128 Mb device
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Sheet
Revision A6 (May 11, 2006)
Add new OPNs, supporting Industrial temperature
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of thirdparty rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2005-2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
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